Cadence Design Systems, Inc. (NASDAQ: CDNS) customers have completed more than 200 tapeouts using the Tempusâ¢ Timing Signoff Solution, the company said.
Since its introduction in the fall of 2013, nearly 100 customers have deployed the solution on a wide range of production designs, from mixed-signal chips to high-speed processor cores to large 100M+-instance systems on chip (SoCs), across mature process nodes and advanced FinFET nodes.
The CadenceÂ® Tempus Timing Signoff Solution includes parallelized computation and physically aware timing optimization capabilities that enable designers to reduce time to signoff closure by significantly reducing engineering change order (ECO) iterations by an order of magnitude.
Using the multi-threaded and distributable path-based analysis (PBA) capability, customers can also analyze thousands of critical paths in their design in a matter of minutes while eliminating hundreds of pessimistic violations reported otherwise by traditional static timing-analysis methods.
The Tempus Timing Signoff Solution is a silicon-accurate, color-aware timing signoff and signal integrity analysis tool that supports advanced-node design requirements for waveform propagation, Miller Effect, ultra-low power, and variation associated with multi-patterning technologies.
Cadence enables global electronic design innovation and plays an essential role in the creation of today´s integrated circuits and electronics. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry.