Ayar Labs Executive Leadership Team Adds Senior Vice President of Engineering

Ayar Labs has announced that Dr. Ken Chang, former VP of Wired Engineering at Xilinx, has joined as Senior Vice President of Engineering, the company said .

Dr. Chang joins Ayar after nine years at Xilinx where he led its SerDes technology group, which delivered industry first 28G KR/CR compliant transceivers for FPGAs and 56G PAM4 and 112G PAM4 transceivers capable of long reach transmission. Prior to that, he was at Rambus for 11 years where he led the development of numerous products and advanced technology development projects, all in the high-speed links domain.

Dr. Chang, an IEEE fellow since 2018, brings a wealth of industry and research experience to Ayar Labs. He has authored or co-authored over 50 technical papers in ISSCC, VLSI, A-SSCC, and JSSC in the area of chip-to-chip interfaces and chip-to-memory. He is also active in the IEEE community and recently served as the technical program chair and co-chair of the VLSI Circuit Symposium in 2018 and 2017, respectively, and served on the Technical Program Committee since 2009. He also served on the Technical Program Committee of ISSCC from 2011-2016 and CICC from 2008-2010.

Dr. Chang holds a B.S degree from National Taiwan University and M.S. and Ph.D. degrees from Stanford University, all in Electrical Engineering.

Ayar Labs is disrupting the traditional performance, cost, and efficiency curves of the semiconductor and computing industries by driving a 1000x improvement in interconnect bandwidth density at 10x lower power. Ayar Labs´ patented approach uses industry standard cost-effective silicon processing techniques to develop high speed, high density, low power optical based interconnect “chiplets” and lasers to replace traditional electrical based I/O. The company was founded in 2015. For more information, visit http://www.ayarlabs.com.